Skip to content
GitLab
Explore
Sign in
Primary navigation
Search or go to…
Project
T
TL-Verilog-VSCode
Manage
Activity
Members
Labels
Plan
Issues
Issue boards
Milestones
Wiki
Requirements
Code
Merge requests
Repository
Branches
Commits
Tags
Repository graph
Compare revisions
Snippets
Locked files
Deploy
Releases
Container registry
Model registry
Monitor
Incidents
Analyze
Value stream analytics
Contributor analytics
Repository analytics
Code review analytics
Issue analytics
Insights
Model experiments
Help
Help
Support
GitLab documentation
Compare GitLab plans
GitLab community forum
Contribute to GitLab
Provide feedback
Keyboard shortcuts
?
Snippets
Groups
Projects
This project is archived. Its data is
read-only
.
Show more breadcrumbs
Dmytro Bogatov
TL-Verilog-VSCode
Repository graph
Repository graph
You can move around the graph by using the arrow keys.
master
Select Git revision
Selected
master
default
protected
1 result
Select display option
Display full history
Display full history
Display up to revision
Created with Raphaël 2.2.0
29
Jul
23
20
11
10
2
1
Fix.
master
master
Fix.
Publish in CI.
Fix.
Fix.
Fix.
Fix.
Prepare to publish.
Fix alignment.
Improvements.
Fix.
Version.
Fixes.
Make light theme.
Basic coloring.
Add theme.
Fix.
Add CI.
Fix. Make it work.
Inital commit.
Loading