TL-Verilog support for VSCode

TL-Verilog support inspired by SystemVerilog extension.

Features

Done

• Syntax highlighting for .tlv .TLV files

Known bugs

• None so far
• Open the issue in one of the repos

Git repos

• Personal, main: dbogatov/TL-Verilog-VSCode
• GitHub, mirror: Dima4ka/tlv-vscode

Repository organization

This repository is organized as follows:

sytnaxes/                     syntax definition
snippets/                     code snippet
src/                          source code for custom feature
language-configuration.json   language configuration
package.json                  package configuration
LICENSE.txt                   license
README.md                     readme

Contributing

1. Fork it ( Dima4ka/tlv-vscode )
2. Create your feature branch (git checkout -b my-new-feature)
3. Commit your changes (git commit -am 'Add some feature')
4. Push to the branch (git push origin my-new-feature)
5. Create a new Pull Request

See also

TL-Verilog

License

MIT