Skip to content
GitLab
Explore
Sign in
Primary navigation
Search or go to…
Project
T
TL-Verilog-VSCode
Manage
Activity
Members
Labels
Plan
Issues
Issue boards
Milestones
Wiki
Requirements
Automate
Agent sessions
Code
Merge requests
Repository
Branches
Commits
Tags
Repository graph
Compare revisions
Snippets
Locked files
Deploy
Releases
Container registry
Model registry
Monitor
Incidents
Analyze
Value stream analytics
Contributor analytics
Repository analytics
Code review analytics
Issue analytics
Insights
Model experiments
Help
Help
Support
GitLab documentation
Compare GitLab plans
GitLab community forum
Contribute to GitLab
Provide feedback
Keyboard shortcuts
?
Snippets
Groups
Projects
This project is archived. Its data is
read-only
.
Show more breadcrumbs
Dmytro Bogatov
TL-Verilog-VSCode
Commits
2f621b93
Commit
2f621b93
authored
Jul 23, 2017
by
Dmytro Bogatov
💕
Browse files
Options
Downloads
Patches
Plain Diff
Fix alignment.
parent
804b5106
No related branches found
No related tags found
Loading
Changes
3
Show whitespace changes
Inline
Side-by-side
Showing
3 changed files
package.json
+1
-1
1 addition, 1 deletion
package.json
syntaxes/tlverilog.tmLanguage
+17
-2
17 additions, 2 deletions
syntaxes/tlverilog.tmLanguage
themes/tlverilog-color-theme.json
+8
-1
8 additions, 1 deletion
themes/tlverilog-color-theme.json
with
26 additions
and
4 deletions
Loading
Preview
0%
Loading
Try again
or
attach a new file
.
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Save comment
Cancel
Please
sign in
to comment