Skip to content
GitLab
Explore
Sign in
Primary navigation
Search or go to…
Project
T
TL-Verilog-Atom
Manage
Activity
Members
Labels
Plan
Issues
Issue boards
Milestones
Wiki
Requirements
Code
Merge requests
Repository
Branches
Commits
Tags
Repository graph
Compare revisions
Snippets
Locked files
Build
Pipelines
Jobs
Pipeline schedules
Test cases
Artifacts
Deploy
Releases
Container registry
Model registry
Operate
Environments
Monitor
Incidents
Analyze
Value stream analytics
Contributor analytics
CI/CD analytics
Repository analytics
Code review analytics
Issue analytics
Insights
Model experiments
Help
Help
Support
GitLab documentation
Compare GitLab plans
Community forum
Contribute to GitLab
Provide feedback
Keyboard shortcuts
?
Snippets
Groups
Projects
This is an archived project. Repository and other project resources are read-only.
Show more breadcrumbs
Dmytro Bogatov
TL-Verilog-Atom
Commits
217cc0b8
Verified
Commit
217cc0b8
authored
7 years ago
by
Dmytro Bogatov
Browse files
Options
Downloads
Patches
Plain Diff
Prepare 0.4.0 release
parent
5b65df92
Loading
Loading
No related merge requests found
Changes
1
Show whitespace changes
Inline
Side-by-side
Showing
1 changed file
package.json
+1
-1
1 addition, 1 deletion
package.json
with
1 addition
and
1 deletion
Loading
Preview
0%
Loading
Try again
or
attach a new file
.
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Save comment
Cancel
Please
register
or
sign in
to comment
